IO-Link Master Module und In-Design-Solution

Overview of IO-Link Master Module und In-Design-Solution

• Complete and tested solution (Ready to Use)
• Quick market launch
• Proven quality
• Pre-certified
• Scalable with different number of ports
• Realized with STM32F411RCT6 and MAX14819
• Available as a hardware module (4 or 8 ports) or as a design template

The solutions contain all necessary functions for a complete IO-Link Master V1.1 including data storage.

The hardware module can be used for evaluation as well as for specific solutions and is available as 4 or 8 port version. The firmware is pre-installed and can be updated via the SPI interface. The driver software for the host controller (TMG TE SPIAPI) is provided as ANSI-C source code. For the IO-Link Master module we also provide the test report for the manufacturer's declaration.

For the In-Design-Solution we provide the circuit diagram (schematic) of our IO-Link Master Module so that it can be integrated into your own devices. If the circuit diagram (schematic) is implemented exactly, our firmware can be used unchanged and the test report can also be referenced here for the manufacturer's declaration. The driver software for the host controller (TMG TE SPIAPI) is delivered as an ANSI-C source code.

Interface between IO-Link Master Module and the host controller (Host Lib)

The interface is based on SPI (sum telegram) communication. The host library is delivered as ANSI-C source code and can be ported easily to different host controllers.

Host controller requirements:

• SPI interface (4 pins)
• DMA for send and receive (recommended)
• Code: for example with Cortex-M processors 8 kByte
• Ram: 4 kByte (for 8 Ports)

Technical Data

• STM32F411RCT6
• MAX14819 (1, 2 or 4 x 2 Port IO-Link Master Transceiver)
• 32kByte EEPROM for non volatile data (data storage)
• TMG IO-Link Master Stack V1.1
  • Including Parameter server (data storage)
  • IO-Link cycle time 0,6 ms
  • All bit rates (230,4k / 38,4k / 4,8K)
  • All Frame types supported
  • Power On/Off per Port
• IO Ports for Pin2 (I/O or diagnostic)
• Firmware download over SPI interface
• TMG TE SPIAPI Interface